m6mgb/t33bs8awg - p renesas lsis 33,554,432 - bit (2,097,152 - word by 16 - bit) cmos flash memory & 8,388,608 - bit (524,288 - word by 16 - bit) cmos sram stacked - csp (chip scale package) rev.0.2_48a_bebz 1 preliminary notice: this is not a final specification. some parametric limits are subject to change. pin configuration (top view) the m6mgb/t33bs8awg - p is a stacked chip scale package (s - csp) that contents 32m - bit flash memory and 8m - bit sram in a 66 - pin stacked csp with leaded solder ball. 32m - bit flash memory is a 2,097,152 words, single power supply and high performance non - volatile memory fabricated by cmos technology for the peripheral circuit and dinor (divided bit - line nor) architecture for the memory cell. all memory blocks are locked and can not be programmed or erased, when f - wp# is low. using software lock release function, program or erase operation can be executed. 8m - bit sram is a 524,288 words asynchronous sram fabricated by cmos technology. the m6mgb/t33bs8awg - p is suitable for a high performance cellular phone and a mobile pc that are required to be small mounting area, weight and small power dissipation. access time flash 70ns (max.) sram 85ns (max.) supply voltage f - vcc =vcc=2.7 ~ 3.0v ambient temperature ta= - 40 ~ 85 c package 66 pin s - csp ball pitch 0.80mm outer - ball: sn - pb application mobile communication products description features 1 2 3 4 5 6 7 8 a b c d e f g h j k l m 8.0 mm 11.0 mm f - vcc : vcc for flash memory s - vcc : vcc for sram f - gnd : gnd for flash memory s - gnd : gnd for sram a0 - a18 : common address for flash/sram f - a19 - f - a20 : address for flash dq0 - dq15 : data i/o f - ce# : flash chip enable s - ce1# : sram chip enable1 s - ce2 : sram chip enable2 f - oe# :output enable for flash s - oe# :output enable for sram f - we# :write enable for flash s - we# :write enable for sram f - wp# : write protect for flash f - rp# :reset power down for flash f - ry/by# :flash ready/busy s - lb# :lower byte control for sram s - ub # :upper byte control for sram nc nc nc a5 a4 a0 f - ce# f - gnd f - oe# nc nc nc a18 a17 a7 a6 a3 a2 a1 s - ce1# s - lb# s - ub# s - oe# dq9 dq8 dq0 dq1 f - wp# nc f - a19 dq11 dq10 dq2 dq3 s - gnd f - rp# dq12 s - ce2 s - vcc f - vcc f - we# f - ry/by# dq13 dq6 dq4 dq5 a16 a8 a10 a9 dq15 s - we# dq14 dq7 nc nc f - a20 a11 a15 a14 a13 a12 f - gnd nc nc nc nc:non connection index(laser marking) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
m6mgb/t33bs8awg - p renesas lsis 33,554,432 - bit (2,097,152 - word by 16 - bit) cmos flash memory & 8,388,608 - bit (524,288 - word by 16 - bit) cmos sram stacked - csp (chip scale package) rev.0.2_48a_bebz 2 preliminary notice: this is not a final specification. some parametric limits are subject to change. capacitance mcp block diagram note: in the data sheet there are ? vcc ? s which mean ? f - vcc ? . in the sram part there are ? ub# ? and ? lb# ? which mean ? s - ub# ? and ? s - lb# ? , respectively. min. typ. max. cin input capacitance a20-a0, f-oe#, s-oe#,f-we#, s-we#,f- ce#, f-wp#, f-rp#, s-ce1#, s-ce2, s-lb#, s-ub# 18 pf cout output capacitance dq15-dq0,f-ry/by# 22 pf symbol conditions ta=25c, f=1mhz, vin=vout=0v unit limits parameter a0 to a20 a0 to a20 f-wp# f-rp# s-we# s-oe# s-ub# s-lb# dq0 to dq15 32mbit dinor flash memory f-vcc f-gnd f-ce# 8mbit sram s-vcc a0 to a18 s-ce1# s-ce2 s-gnd f-we# f-oe# f-ry/by# www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
m6mgb/t33bs8awg - p renesas lsis 33,554,432 - bit (2,097,152 - word by 16 - bit) cmos flash memory & 8,388,608 - bit (524,288 - word by 16 - bit) cmos sram stacked - csp (chip scale package) these materials are intended as a reference to assist our custom ers in the selection of the renesas technology corporation product best suited to the customer's ap plication; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporation or a third party. renesas technology corporation assumes no responsibility for any damage , or infringement of any third - party's rights, originating in the use of any product data, diag rams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents infor mation on products at the time of publication of these materials , and are subject to change by renesas technology corporation without notice due to product improvemen ts or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product informati on before purchasing a product listed herein. the information described here may contain technical inaccuracie s or typographical errors. renesas technology corporation assumes no responsibility for any damage , liability, or other loss rising from these inaccuracies or err ors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page ( http://www.renesas.com ). when using any or all of the information contained in these mate rials, including product data, diagrams, charts, programs, and a lgorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage , liability or other loss resulting from the information contain ed herein. renesas technology corporation semiconductors are not designed or manuf actured for use in a device or system that is used under circums tances in which human life is potentially at stake. please conta ct renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, su ch as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. if these products or technologies are subject to the japanese ex port control restrictions, they must be exported under a license from the japanese government and cannot be imported into a coun try other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan an d/or the country of destination is prohibited. please contact renesas technology corporation for further details on these materials o r the products contained therein. renesas technology corporation puts the maximum effort into making semi conductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage.remember to give due co nsideration to safety when making your circuit designs, with app ropriate measures such as (i) placement of substitutive, auxilia ry circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials keep safety first in your circuit designs! rej03c0160 ? 2003 renesas technology corp. new publication, effective april 2003. specifications subject to change without notice nippon bldg.,6 - 2, otemachi 2 - chome, chiyoda - ku ,tokyo,100 - 0004 japan www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com
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